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Difference between revisions of "FPGAWeek12Exercise"

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*** Add the existing .vhd and .ucf sources from the frequency counter reference design folder that you unzipped
*** Add the existing .vhd and .ucf sources from the frequency counter reference design folder that you unzipped
*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
***  
*** A portion of the design uses a undocumented mode of operation for the S3E DCM.  Instructions for enabling this can be found in the dcm_fixed_osc.vhd file.  They are excerpted as follows:
*** ASDF
**** This design is for SPARTAN-3E devices only. Special set up required to process this design with ISE tools.
*** ASDF
**** On Windows: Set an environment variable called XIL_TEST_ARCS - My_computer -> properties -> advanced -> Environment variables  System variables -> New ->  XIL_TEST_ARCS with value = 1 - Make sure the Xilinx tools are closed and opened again before using.
*** ASDF
*** Once the variable has been set, close ISE and restart it.
** asdf
*** Select the top level module, and take it through the implementation process - synthesis, place and route, generate programming file.
** asdf
*** Use impact to program the .bit file to the FPGA!  It should
** Implementing the frequency generator
*** In the frequency generator folder, there is a pdf.  It is the readme for the project.  It will be your friend - it details how to quickly run the project, setup the ISE project, design details for the hardware and picoblaze software, and some more project ideas.
*** In ISE, create a new design called "s3e_ref_freq_ref" in your ~/Projects directory.
*** Add the existing .vhd and .ucf sources from the frequency ref reference design folder that you unzipped
*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
*** A portion of the design uses a undocumented mode of operation for the S3E DCM.  Instructions for enabling this can be found on page 13 of the Frequency generator documentation.
*** Afer this is done, you should be able to implement this design and program the FPGA with impact.
** asdf
** asdf
** asdf
** asdf

Revision as of 18:39, 30 December 2009

  • Download the Frequency Counter and Frequency Generator reference designs from http://www.xilinx.com/products/boards/s3estarter\/reference_designs.htm
  • Download the Picoblaze processor core from http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm
  • Unzip these projects & picoblaze source to your ~/Projects directory (or appropriatlely)
  • Implementing the projects directly
    • Each project comes with a .bit file that you can use to program the FPGA starter kit with. Use impact to program the chip.
    • On Windows, you can run the install batch scripts to run impact automatically
  • Implementing the projects through ISE
    • Implementing the frequency counter
      • In the frequency counter folder, there is a pdf. It is the readme for the project. It will be your friend - it details how to quickly run the project, setup the ISE project, design details for the hardware and picoblaze software, and some more project ideas.
      • In ISE, create a new design called "s3e_ref_freq_count" in your ~/Projects directory.
      • Add the existing .vhd and .ucf sources from the frequency counter reference design folder that you unzipped
      • Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
      • A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found in the dcm_fixed_osc.vhd file. They are excerpted as follows:
        • This design is for SPARTAN-3E devices only. Special set up required to process this design with ISE tools.
        • On Windows: Set an environment variable called XIL_TEST_ARCS - My_computer -> properties -> advanced -> Environment variables System variables -> New -> XIL_TEST_ARCS with value = 1 - Make sure the Xilinx tools are closed and opened again before using.
      • Once the variable has been set, close ISE and restart it.
      • Select the top level module, and take it through the implementation process - synthesis, place and route, generate programming file.
      • Use impact to program the .bit file to the FPGA! It should
    • Implementing the frequency generator
      • In the frequency generator folder, there is a pdf. It is the readme for the project. It will be your friend - it details how to quickly run the project, setup the ISE project, design details for the hardware and picoblaze software, and some more project ideas.
      • In ISE, create a new design called "s3e_ref_freq_ref" in your ~/Projects directory.
      • Add the existing .vhd and .ucf sources from the frequency ref reference design folder that you unzipped
      • Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
      • A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found on page 13 of the Frequency generator documentation.
      • Afer this is done, you should be able to implement this design and program the FPGA with impact.
    • asdf
    • asdf
    • asdf