From HacDC Wiki
1) Introduction to digital logic & design
2) Verilog HDL modeling & testing
3) FPGA's & using them.
We will be taking an approach of reviewing & learning digital design, implementing designs and methods of formally simulating and verifying designs before moving into FPGA oriented work. This workshop will be more engineering oriented than hobbyist/tinkerer oriented.
We'll be covering some FPGA specific topics and projects using real hardware. The first half of the workshop will cover logic design, implementation and testing. This will allow people to put off ordering any hardware until they know that they actually want to pursue FPGA development, since the dev board I've chosen for this is not cheap but I feel is robust enough to be a good starting board for this group.
The hardware we'll be using is the Xilinx Spartan 3AN development kit. This kit is available from a few vendors for 199USD + shipping. This will be discussed more later on. The kit includes programming cable, and evaluation copies of some of the Xilinx tools."
Verilog Simulation and Waveform Viewing
Icarus verilog & gtkwave; for doing Verilog compilation, simulation and waveform viewing. A makefile has been made to simplify the flow for any exercises and projects we use these tools with. That makefile can be found here.
After we finish up with covering Verilog modeling, we'll move to the Xilinx ISE Webpack tools and actual work with FPGAs. This software is available from Xilinx for free, and is available for Windows and Linux platforms. This will be used for Verilog compilation, simulation, synthesis of designs, design mapping, place and routing of designs, bitstream generation and board programming.
An OpenSuse Virtual Machine (VMWare based) will be available for people to use in this course, if they wish. This will
have the icarus verilog tools and GTKwave loaded on it, along with Firefox, gcc and make. The suseStudio team has encouraged the use of their VMs in such a manner (teaching workshops). This is being built in susestudio, and will be available as a live install as well.
When we move over to the Xilinx tools, people will have to download and install the Xilinx tools by themselves, since that material is copyrighted. Instructions will be given for doing that.
The VMware VM image is ready (ver 0.5.2) for people to grab if they wish. Get it here. There are a few items of note regarding the VM
- The download link is a virgin, freshly built VM, so you'll be the first user booting it up since build.
- There are two users, root and workshop. Both have the password 'linux'
- For the user workshop, ~/scripts/ is included in their $PATH
- Also, user workshop has a few small files in ~/resources/ including a simple upcounter design example.
- May need to run the network configuration tools to ensure you get functional networking. I've experienced issues with the VM in suspend mode, switching networks on the host machine, and completely loosing network on the VM until rerunning the network config tools. They can be found poking around in the system settings for yast.
- Currently, the Xilinx Cable Drivers aren't building on the VM (but all the other Xilinx tools work). If someone is a linux guru and wants to try to make it work, contact me at teachmeFPGA@gmail.com. My next attempt is to turn the vm into a live-install and try building the cable drivers on real hardware instead of a VM.
- After loading the Xilinx settings (which will be covered in more detail when those tools are introduced), the current shell can no longer run icarus verilog flows. Start a new shell in order to run icarus verilog.
- Its a fairly minimalist system, with the FOSS tools listed above load, along with firefox, gcc and nano. Use yast or yast2 in order to install any additional packages. example yast2 --install packname
- If the download link stops working, the build has expired on the SuseStudio server. Please email teachmeFPGA@gmail.com if the download link no longer works.
- Mad props to the susestudio team for making this possible
Lecture/Discussions will mainly be based on content from a pair of courses in MIT's Opencourseware initiative. This content is licensed on the Creative Commons Attribution NonCommercial Share-alike 3.0 license; as a result, the electronic content generated by the workshop will also need to be made available under the same license. This will allow people to freely access just the discussion slides without watching through videos.
A video archive will be made available for those unable to attend.
List of Lectures
This is currently an incomplete list, additional topics will be added as I solidify them - wgibb
|1||October 7th, 2009||Workshop Introduction & Introduction to digital systems and design||Make sure people can run the Virtual Machine or FOSS tools|
|2||October 14th, 2009||Boolean Logic, combinatorial circuits and timing||Make sure people can run the Virtual Machine or FOSS tools|
|3||October 21st, 2009||Introduction to Verilog Coding, focusing on combinatorial circuits||Verilog Coding - Modular Full Adder Design and Simulation|
|4||October 28th, 2009||Digital Arithmetic and adder styles||Implement various adders, static gate delays & modeling their timing effects|
|5||November 11th, 2009||Introduction to Sequential Logic and Flip-Flops||Modeling & Simulation of Flip Flops and simple Sequential Logic|
|6||November 18th, 2009||Finite State Machines & You||Modeling of Finite State machines|
|7||November 25th, 2009||Testbenches in Verilog||Practical FSM Exercise, event driven testbench|
|8||December 2nd, 2009||Introduction to FPGAs - History, Capabilities and Features||Load up Xilinx Tools & conversion of past exercises into ISE Projects, time permitting|
|9||December 9th, 2009||Logic Synthesis & Design considerations with FPGAs||Conversion of projects, simulation in iSim|
|10||December 16th, 2009||TBD||TBD|
This workshop will be free of charge to attend, but there are additional needs in order to fully benefit from attending the workshop.
- Open mind to learning
- Willingness to read documentation, as the capacity for independent research is important for doing hardware design.
- Willingness to commit time over this fall
- Either ability to run a VMWare virtual machine, the ability to convert the VM for virtualBox, or ability to install the icarus verilog/gtkwave tools on your own. This will likely necessitate a laptop of some sort.
- Xilinx.com account, for licensing Xilinx tools and IP.
- Hardware will NOT be required at the beginning of the course but will be needed later on to run exercises and to do any interesting projects
Workshop Frequently Asked Questions
- What operating systems will the FPGA toolchain be available on?
- The Xilinx ISE Webpack is supported on Windows XP Pro, Windows Vista Business, Redhat Linux and Suse Linux Enterprise. For a detailed list of official OS support, check out the Operating system support page on Xilinx.com. The tools will run on openSuse as well. Feel free to try other linux distros and post your results.
- What is the cost of the FPGA development board we'll be using?
- The retail cost of the development board is typically around 199-220 USD, plus shipping, from a few different vendors. Links for that are here.
- Will there be homework?
- Since this isn't an academic course, there will not be graded homework in the traditional sense. I'll be choosing a few additional exercises that people can do outside of the workshop each week, if they wish, that will further help hone their skills.
- Will there be extensive C/C++ coding?
- C experience is not a prerequisite for this workshop. There will not be any C/C++ coding involved in the workshop directly. There is one project that I've got in mind that may be of interest to people that are proficient in C/C++ and pick up hardware design rather well.
William Gibb, mad scientist. For contacting him regarding the workshop, please email teachmeFPGA@gmail.com.
Grateful Dead Trees Reference
Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog by Lee
FPGA Prototyping using Verilog Examples by Chu.
These texts will not be required for the course, but are very good launching points for the topics that we are covering.
Xilinx Design Tools
VMware Player - Free download for Windows and Linux
SUSE Studio SLED/OpenSUSE build service. Make VMs, live installs, all customized
Convert VMware VMs to VirtualBox vms (only works on VMDK files, not VMX) untested by course instructor
Spartan 3AN Starter Kit
Open Circuit Design Open Source design tools
Doulos Digital Design Resources Good learning and design references
ASIC World Good learning references
FPGA4Fun Lots of available IP
Companion website for Professor Pong Chu's Verilog Book
OpenCores Very good repository for IP. Also the home to the OpenRISC System on Chip project